What are the most effective ways to reduce the size of integrated circuits?

1. Floorplanning is the key. 2. Circuit engineers play a major role in the layout floorplan. The Schematic hierarchies should be layout floorplan friendly. 3. The Layout Designer need to give feedback to circuit team in case the schematic hierarchy does not make sense and results into bad floorplan and hence scenic routing. 4. Collaboration between Circuit and Layout Teams. Both work towards a common goal, but should take parallel steps to make the design journey more meaningful.

Even in the analog domain we should look to use smaller transistors. Rule 1, never break the design rules, they are there to prevent all the things you don’t know about. Precision circuits don’t have to be huge, careful optimization using Monte Carlo simulations to try things out. Wiggle everything to ensure that your solution is the smallest. Consider using auto zero techniques to shrink transistor requirements (adding it can shrink your physical design). Circuits do get more complex, but all the components may be small (hold capacitors now become the largest components.

1. The most important is the layout floorplan! 2. Build eficient circuit design - obtain the function needed with minimum gates! 3. Build circuits that can be used by different blocks at different time like BIU ( Bus Interface Units) 4. Plan central busses that can be used at different times by different communication between blocks! For more read my book !

1. Build this was the reason for ASIC instead of ASSP. Make the chip contain ONLY the circuits required for a specific usage/function, so the content is minimal! Have a strong technical marketing that can define what is needed not what “it could” be needed! 2. Hire design teams that can find solutions with minimum steps and build them optimized for the specifications! A pacemaker has a different lifetime requirements than a Fitbit device ! Same for chips for airplane versus cars, different tolerance levels! 3. Use circuit solutions that can be reused by different applications at different times. 4. Use the most advance package that offers flip chip capabilities, so IO area is minimal. 5. Floorplan, floorplan and floorplan!

Assuming that circuit is fixed. Although, measures can be taken at the circuit design side to reduce the area. Here are the ways to reduce the IC size from layout point of view: 1. Do maximum sharing of the diffusion of transistors. 2. Using isolations, we can compactly place analog and digital blocks near leading to area saving. 3. Using dual patterning we can do compact routing. 4. MOSFET based resistances and caps can be used. 5. We can effectively break transistors into fingers and multipliers and arranged them effectively to save the area. 6. Where ever possible sharing of the base layers could be done to save area. 7. Follow tight DRC rules. 8. & so on...

Advanced EUV based technologies have colored Metals in layout. Layout Designers should invest time in understanding the DRCs between same/different colors for various widths. At times, I have found a mix match combination working out better in the Digital domain.

In addition to the points in the above section ++ 5. Not all signals need wide tracks, and many static signals can be used for shielding. Conversations on these help optimizing metal limited design. Avoid over-designs, but still Beat the specs. 6. Be friends with your design. The more you know it, the better you can optimize it at all levels. Some Layout based optimizations reflect quality improvement on Silicon. Tools can't model all of these until PDKS are LDE aware.

I see advanced packaging as an emerging and essential element as the cost of traditional scaling continues to rise. This includes both 3D and 2.5 D packaging techniques.

In my experience, classic design-reuse, may lead to increased size as blocks often have to implement a wide range of features things to maximise reusability. Hard-macro blocks (i.e. pre-layed-out) can be efficient for the block but cause routing complexity and restrict optimization of the rest of the design. RTL-level code reuse can improve on this by using configuration parameters to simply not implement some features of the reusable block. For DSP-style functions, high-level synthesis approaches (e.g. from C) can add benefits as they can allow designers to focus an implementation on size, power and/or latency and to experiment relatively quickly.

Be watchful for design-reuse. Instead of compromising on the design PPA by as-is reuse, use the existing reference as the starting point. You will still get reduced design time. Design reuse is applicable even at lower design hierarchies; using tool features like clones and synchronous clones can even help in design re-use for routings, TAPs, boundary cells and other non-device layout elements.

In analog ICs, a significant area is used by passive components, mainly capacitors. Minimizing these, using a process with high density capacitors, stacking MIM type capacitors over circuitry are among efficient options. Keeping circuit as simple as possible is also a source of area reduction.

In ASIC design, the usage of multibit flops helps us to reduce the area and also power as well. Some of the tools support the multibit optimization starting from the front end stage itself. In the case of Custom IC design, the reduction of parasitics in the design and identifying the root cause of that might helps us to reduce the overall delay and area eventually.

The size of an IC is largely determined by its architecture. If you can customize the design (ASIC) to more closely match the product requirements then you can reduce the die size. Smaller geometry processes can be more expensive to design and manufacture so it maybe better to look at cost rather than die size alone. If you have analog components then they often do not shrink in the same way as digital and hence driving towards smaller geometries doesn't always provide the die size reduction you might expect.

There are 2 approaches to shrinking die sizes. The expensive way, reducing feature sizes, or the innovation route. Sometimes, particularly with digital circuits the former is the only real option. In the analog domain innovation is key. An analog circuit innovator can be worth a fortune in increased margins and yet are often misunderstood and treated poorly. If as a designer you are not there yet, practice, practice, practice. Never accept the first solution unless you have rejected all the others. DO MULTIPLE SOLUTIONS.!!! Iterate small improvements, sometimes they end up big improvements.

Many area wasteful techniques remain in the analog domain. The chief area that still persists is the centralized bias generator. This is a hangover from the days when resistors were huge (when we did not have high res poly). Making low bias currents ended up as huge circuits. Chips were also less complex. The problem is that as bias necessarily get lower sensitivity gets higher, and crosstalk becomes a real problem. The layout guys add guard traces around each bias line to prevent issues and now the trace area is huge, the capacitance is huge and startup times get much longer than simulated. Get rid of the bias generator, do local or in-cell bias and end up with predictable smaller designs.