What are the best practices for applying clock gating at different levels of design hierarchy?

1 RTL level

At the RTL level, you can use behavioral or structural clock gating to control the clock enable signals for your registers and flip-flops. Behavioral clock gating involves conditional statements or expressions to determine when the clock is enabled or disabled, while structural clock gating utilizes dedicated clock gating cells or modules with a clock input, output, and enable input. Both methods have their own benefits and drawbacks depending on design complexity, coding style, and synthesis tool. When using RTL level clock gating, it's important to use consistent and clear naming conventions for clock enable signals and gating cells or modules. In addition, complex or nested conditional statements or expressions should be avoided to prevent synthesis issues or timing violations. Furthermore, you should use clock gating cells or modules that are compatible with your target technology and library, and verify the functionality and timing of your design with simulation and formal methods.

2 Synthesis level

At the synthesis level, you can use either automatic or manual clock gating to optimize your design for power and area. Automatic clock gating is performed by the synthesis tool, which identifies and inserts clock gating cells or modules based on the logic and data dependencies of your registers and flip-flops. Alternatively, manual clock gating can be done by the designer, who specifies the clock gating cells or modules and their locations using constraints or directives. Both methods have their advantages and disadvantages depending on the design size, quality, and accuracy. Generally speaking, automatic clock gating should be used for large or complex designs that have many opportunities for power reduction and area saving, while manual clock gating should be used for small or simple designs that have few or specific opportunities for power reduction and area saving. Additionally, synthesis options and reports should be used to control and evaluate the clock gating results and trade-offs, while synthesis constraints and directives should be used to guide and refine the clock gating process in order to avoid unwanted changes or errors.

3 Physical design level

At the physical design level, placement or routing clock gating can be used to fine-tune a design for power and timing. Placement clock gating is done by the placement tool, which assigns and locates clock gating cells or modules based on the proximity and connectivity of the clocked elements. Routing clock gating is done by the routing tool, which adds or removes the clock gating cells or modules based on the wire length and congestion of the clock network. Each method has its own advantages and disadvantages depending on the design density, variation, and reliability. Generally speaking, placement clock gating should be used for high-density or low-power designs that have tight timing and area constraints, while routing clock gating should be used for low-density or high-performance designs that have flexible timing and area constraints. Additionally, placement and routing options and reports can help monitor and verify the impact of clock gating while placement and routing constraints and directives can help prevent and correct any issues or violations.

4 Here’s what else to consider

This is a space to share examples, stories, or insights that don’t fit into any of the previous sections. What else would you like to add?