What are the best practices for layer stackup in high-speed PCB design?

Since this is a high-speed design article, I will just say that the entry-level stackup for most high-speed designs will be a 4 layer stackup with a SIG+PWR/GND/GND/SIG+PWR arrangement. I have done SIG/GND/PWR/SIG in power systems that also have an MCU with fast signals on the top layer, but this is less common. In some cases you can do a high-speed design on two layers, but you need to have coplanar ground around signal lines in order to make up for the lack of a ground plane, especially around differential pairs. This is the reason that, for example, USB can work on two layers, even at the faster standardized speeds in newer generations.

For Complex High speed boards with large BGA's, the number of layers is based on: *Count of largest BGA signals. *Fan out method, PTH or laser & buried Vias, will define the BGA escape channels. *Trace count per BGA channel (depends on BGA pitch, Via diameter & trace width/space and diff pairs). *Assuming BGA signals can escape away from 4 BGA sides, the total trace count can be divided by 4 and further by number of traces that can escape through all side channels. This will result with minimal layers required only for signals! Recommend to add at least one additional signal layer. *Each pair of signals has to be covered with one continuous GND plane and one power plane. *Finally add 2 external layers. Check the final PCB thickness.

Well the number of layers also depends on depth of the BGA's used and number of differential signals and there match length requirements and some mixed signals board have layer restrictions so consume more layers for high speed boards shielding ground layer also required to control signal impedance ,some boards have dedicated signals while some has option for signal assignments which consumes less layer ,some boards have stitching vias and shielding requirements which takes more space and hence consume more layers.

In theory orthogonal routing for dual strip line geometry will reduce coupling but in practice for high density routing it is difficult to prevent sections of parallel coupling on adjacent layers. Since cross talk is rise time dependent the coupled length reduces as rise times get faster.

Substrates that are not true random weave can exhibit strong dielectric anisotropy - i.e. they have different dielectric constants in X and Y directions. This is not so much of a problem these days, but it's something to be aware of. This effect can be measured by test resonators, an elongated ring printed at different angles will give a measure of this. Ring resonators are very useful for checking the dielectric constant and should be included on any serious microwave board. A ring is preferred as there is no capacitive fringing end effect. The resonators should be lightly coupled to minimise frequency shifting due to loading. This and a TDR of a test line (which can be extracted from s-parameter) will ensure good performance.

The advice listed by the AI is just "impedance is important." What most people describe as "controlled impedance" is really "controlled dielectric," they are two different things. What the AI has done here is try to describe a controlled dielectric approach, where the designer picks the specific materials by calling out a vendor's product in their stackup and calculating the trace width based on the Dk value. Controlled impedance is where the designer specifies a specific trace width and impedance value requirement, and the manufacturer mixes & matches layers until they get as close as possible to your values. They will also test for impedance with a TDR.

In a controlled impedance design, the PCB fab shop manages the fabrication process to ensure that the traces meet specified impedance targets. Once they receive the artwork, they may adjust the line width and space as needed to achieve the target characteristic impedance. To be sure the PCB has been fabricated correctly, the PCB fab shop will design impedance coupons with trace geometries identical to those in the original design and include them on the same panel as the main PCB. After fabrication, they measure the impedance coupons with a Time-Domain Reflectometer (TDR) to confirm that the impedance is within a specified tolerance, typically +/- 10%.

I agree with Lambert, but many times the PCB Fabricator may not be able to adjust the trace widths to meet the target impedances, We ask the fabricator for the stackup during the PCB Design phase, The fabricator will provide the stackup with single ended / differential impedance trace widths for all the layers Sometimes we use PCB fabricator's standard stackup and calculate the trace widths for the target impedances We will also specify the controlled impedance table in the fabrication drawing and ask the fabricator to meet the impedances within the tolerances

Dielectric constant is often anything but. Even RF materials can have a variation of +/- 10%. Closed form equations used by most online calculator are typically only accurate to within 2% - there's 3% design tolerance before you even start. Now add in the etching tolerance. Good news is that unless your match requirements are really severe (>20 dB), anything between 45 to 50 ohms is normally sufficient. Do the calculations (have a look in Pozar).

To ensure minimal crosstalk in high-speed serial links, it's crucial to route the transmit and receive on separate single stripline layers that are adjacent to ground planes. Intra-pair skew length compensation should be done on the same layer prior to changing layers to mitigate mode conversion from differential to common signal. This is especially important when transitioning from package pins to vias on microstrip layers. When changing layers, also make sure to symmetrically place a pair of ground return vias at the same distance relative to the positive/negative signal vias.