What are the best materials and methods for CMOS gate stack engineering in memory devices?

1 Gate electrode materials

The gate electrode is the conductive layer that applies the voltage to the gate dielectric and modulates the channel conductivity. The choice of the gate electrode material depends on several factors, such as the work function, the compatibility with the gate dielectric, the thermal stability, and the resistance to oxidation and diffusion. Traditionally, polysilicon has been used as the gate electrode material for CMOS devices, as it offers good work function tuning, low resistance, and easy integration. However, as the device dimensions shrink, polysilicon faces some limitations, such as increased depletion effects, high resistivity, and dopant segregation. Therefore, alternative materials, such as metal gates and silicides, have been explored to replace polysilicon. Metal gates offer higher conductivity, lower depletion effects, and better compatibility with high-k dielectrics, but they require careful engineering of the work function to match the desired threshold voltage for both n- and p-type devices. Silicides are compounds of silicon and metals that combine the advantages of both materials, such as low resistance, good work function tuning, and thermal stability, but they also pose some challenges, such as increased leakage and interface degradation.

2 Gate dielectric materials

The gate dielectric is the insulating layer that separates the gate electrode and the channel, and determines the capacitance and the leakage of the device. The choice of the gate dielectric material depends on several factors, such as the dielectric constant, the equivalent oxide thickness, the interface quality, and the reliability. Traditionally, silicon dioxide has been used as the gate dielectric material for CMOS devices, as it offers excellent interface quality, low leakage, and high reliability. However, as the device dimensions shrink, silicon dioxide faces some limitations, such as increased tunneling current, reduced capacitance, and degraded reliability. Therefore, alternative materials, such as high-k dielectrics, have been explored to replace silicon dioxide. High-k dielectrics are materials with a higher dielectric constant than silicon dioxide, which allow for a thicker physical layer while maintaining a low equivalent oxide thickness, thus reducing the tunneling current and increasing the capacitance. However, high-k dielectrics also pose some challenges, such as lower interface quality, higher leakage, and lower reliability.

3 Gate stack engineering methods

The gate stack engineering methods are the techniques and processes used to fabricate and optimize the gate stack structure and performance. This includes depositing, annealing, etching, and doping the gate electrode and dielectric materials, as well as integrating the gate stack with the source/drain regions and interconnects. The goals of these engineering methods are to control the work function, reduce resistance, improve interface quality, enhance reliability, and minimize parasitic effects. Common gate stack engineering methods include metal gate electrode deposition (e.g. PVD, CVD, or ALD), high-k dielectric deposition (e.g. ALD, CVD, or MBE), etching (e.g. RIE or plasma etching) to define the gate length and width, and doping (e.g. ion implantation or plasma doping) to modify the work function and improve interface quality.

4 Here’s what else to consider

This is a space to share examples, stories, or insights that don’t fit into any of the previous sections. What else would you like to add?