Synopsys PrimeTime is a powerful tool for performing static timing analysis (STA) of integrated circuits (ICs). STA is the process of verifying that the timing requirements of an IC are met under different operating conditions and variations. In this article, you will learn how to use Synopsys PrimeTime for timing analysis of an IC in six steps.
Before you can use Synopsys PrimeTime, you need to prepare your design files and libraries. You need to have a netlist file that describes the connectivity and functionality of your IC, a constraint file that specifies the timing, power, and area goals and constraints of your design, and a library file that contains the characterization data of the standard cells, macros, and IOs used in your design. You also need to have a link file that defines the search paths for the library files.
Apart from those inputs, users need SPEFs for net delay estimation. Db or liberty files will provide cell delays and timing arc information whereas for net delay, rc corner specific parasitic extraction i.e SPEF is required in order to have an adequate timing session. Also, to allow PT to generate better ECO configuration, users can provide designs of physical information through the def/design Library.
One other thing Primetime can do is read location from the starrcXtract/def and use this physical information further for all the optimization commands. This helps in generating better Timing ECOs causing less of a mess up for the user to clean up after.
PrimeTime? PrimeTime (PT) is a sign-off quality static timing analysis tool from Synopsys. Static timing analysis or STA is without a doubt the most important step in the design flow. It determines whether the design works at the required speed.
1. Launch Synopsys Prime Time software on your computer. 2. Create or open a design file for the IC you want to analyze. 3. Set up the timing constraints for the design, including clock frequency, input/output delays, and other timing requirements. 4. Run the static timing analysis (STA) tool to analyze the timing performance of the design. This will generate a timing report that includes information about setup and hold times, clock skew, and other critical timing parameters. 5. Review the timing report to identify any potential timing violations or areas for improvement in the design.
Prepara??o do Design: Carregue o design do CI no PrimeTime, normalmente em um formato de descri??o de hardware (HDL) como Verilog ou VHDL. Certifique-se de que o design está sintetizado e pronto para a análise de tempo. Setup do Ambiente: Defina o ambiente de simula??o e análise, incluindo as bibliotecas de células, restri??es de temporiza??o, entre outros parametros necessários.
To launch PrimeTime, you need to open a terminal and type the command pt_shell . This will start the interactive mode of PrimeTime, where you can enter commands and view the results. Alternatively, you can use the batch mode of PrimeTime, where you can run a script file that contains the commands you want to execute. To use the batch mode, you need to type the command pt_shell -f script_file , where script_file is the name of your script file.
The next step is to read your design and libraries into PrimeTime. You can use the command read_netlist to read your netlist file, the command read_sdc to read your constraint file, and the command read_lib to read your library file. You can also use the command link to read your link file and automatically load the libraries specified in it. After reading the design and libraries, you can use the command check_design to check for any errors or warnings in your design.
The next step is to set up the analysis mode and conditions for your timing analysis. You can use the command set_operating_conditions to select the operating conditions, such as temperature, voltage, and process corner, for your analysis. You can also use the command set_analysis_mode to choose the analysis mode, such as early, late, min, max, or on_chip_variation, for your analysis. The analysis mode determines how PrimeTime handles the timing variations and uncertainties in your design.
Currently, industry has moved into POCV which is the most advanced form of Timing Analysis. One of the main settings is the sigma setting which quantifies how much of the design the user is trying to converge. The higher the sigma, the higher is the count of violations that need to be addressed.
The next step is to perform the timing analysis using PrimeTime. You can use the command report_timing to generate a timing report that shows the timing paths, delays, slacks, and violations in your design. You can also use the command report_clocks to generate a clock report that shows the clock domains, frequencies, skews, and jitter in your design. You can use various options and filters with these commands to customize the output and focus on the relevant information.
Also, PT can provide a detailed summary of the violations with "report_global_timing" and "report_constraints -all_violators" commands.
Some interesting commands are get_timing_paths which returns timing paths as collections on which users can query attributes- mostly used for scripting and analysis of huge timing buckets. The report_delay_calculation command is used to understand the bad delays at cell or net level. There are other multiple useful switches to report_timing that gives users a holistic picture of why a path is violating.
The final step is to optimize your design using PrimeTime. You can use the command optimize_netlist to perform automatic optimization of your design based on your constraints and analysis mode. This command can perform actions such as resizing, buffering, cloning, and gate cloning to improve the timing, power, and area of your design. You can also use the command report_optimization to generate an optimization report that shows the changes and benefits of the optimization.
Primetime offers a way of analyzing and optimizing the designs at all PVT corners ensuring an optimization in one corner doesn't break the other. This is achieved buy what is known as DMSA where the user can bring up multiple critical PVT corners allat one and query the worst setup/hold timing paths among them.